1. Field of the Invention
The present invention relates to a semiconductor device and a production method therefor, and more particularly to a structure and a production method for an SGT (Surrounding Gate Transistor) which is a vertical MOS transistor comprising a pillar-shaped semiconductor layer having a sidewall serving as a channel region, and a gate electrode formed to surround the channel region.
2. Background Art
With a view to achieving higher integration and higher performance of a semiconductor device, an SGT (Surrounding Gate Transistor) has been proposed which is a vertical transistor comprising a pillar-shaped semiconductor layer formed on a surface of a semiconductor substrate, and a gate formed to surround a sidewall of the pillar-shaped semiconductor layer (see, for example, Patent Document 1: JP 2-188966A). In the SGT, a drain, a gate and a source are arranged in a vertical direction, so that an occupancy area can be significantly reduced as compared with a conventional planar transistor.
FIGS. 46(a) and 46(b) show an SGT disclosed in the Patent Document 1, wherein FIG. 46(a) and FIG. 46(b) are, respectively, a bird's-eye view and a sectional view of the SGT. With reference to FIGS. 46(a) and 46(b), a structure of the SGT will be briefly described below. A pillar-shaped silicon layer 1601 is formed on a silicon substrate. A gate dielectric film 1602 is formed to surround the pillar-shaped silicon layer 1601, and a gate electrode 1603 is formed to surround the gate dielectric film 1602. A lower diffusion layer 1604 and an upper diffusion layer 1605 are formed underneath and in an upper portion of the pillar-shaped silicon layer 1601, respectively. The upper diffusion layer 1605 is connected to an interconnection layer 1606 via a contact.
FIGS. 47(a) to 47(c) show a CMOS inverter using an SGT, wherein FIG. 47(a), FIG. 47(b) and FIG. 47(c) are, respectively, an equivalent circuit of the CMOS inverter, a top plan view of the CMOS inverter, and a sectional view taken along the line B-B′ in FIG. 47(b). Referring to FIGS. 47(b) and 47(c), an N-well 2702 and a P-well 1703 are formed in an upper region of a Si substrate 1701. A pillar-shaped silicon layer 1705 constituting a PMOS transistor (PMOS pillar-shaped silicon layer 1705) and a pillar-shaped silicon layer 1706 constituting an NMOS transistor (NMOS pillar-shaped silicon layer 1706) are formed on a surface of the Si substrate, specifically on respective ones of the N-well region and the P-well region, and a gate 1708 is formed to surround the pillar-shaped silicon layers. Each of a P+ drain diffusion layer 1710 formed underneath the PMOS pillar-shaped silicon layer, and a N+ drain diffusion layer 1712 formed underneath the NMOS pillar-shaped silicon layer, is connected to an output terminal Vout 17. A source diffusion layer 1709 formed in an upper portion of the PMOS pillar-shaped silicon layer is connected to a power supply potential Vcc 17, and a source diffusion layer 1711 formed in an upper portion of the NMOS pillar-shaped silicon layer is connected to a ground potential GND 17. Further, the gate 1708 common to the PMOS and NMOS pillar-shaped silicon layers is connected to an input terminal Vin 17. In this manner, the CMOS inverter is formed.
As a prerequisite to enhancing a channel controllability by a gate in an SGT to sufficiently suppress short-channel effects, it is necessary to form a pillar-shaped silicon layer to have a sufficiently-small size relative to a gate length. A size of a pillar-shaped silicon layer can be reduced in a relatively easy manner, for example, by causing dimensional shrinking during dry etching for forming the pillar-shaped silicon layer, or by performing sacrificial oxidation after formation of the pillar-shaped silicon layer. Thus, in many cases, a pillar-shaped silicon layer is formed to have a size less than a minimum fabrication size F, in order to sufficiently suppress the short-channel effects in an SGT. FIG. 48 shows a structure of an SGT which comprises a pillar-shaped silicon layer 1611 having a size less than the minimum fabrication size F. In this SGT structure, a gate length is sufficiently large relative to the size of the pillar-shaped silicon layer 1611, so that the short-channel effects can be suppressed. Further, a contact 1616 to be formed on a top of the pillar-shaped silicon layer is formed in a similar size to the minimum fabrication size F, so that it will become structurally larger than the pillar-shaped silicon layer 1611.
However, the SGT structure illustrated in FIG. 48 has the following problems. Firstly, in terms of a need for forming a silicide layer on each of upper and lower sides of the pillar-shaped silicon layer to reduce a parasitic resistance in an SGT, a reduction in size of a pillar-shaped silicon layer causes difficulty in forming an adequate silicide on top of the pillar-shaped silicon layer due to the so-called “narrow width effect” on the silicide layer. Moreover, even if an adequate silicide can be formed on top of the pillar-shaped silicon layer, an interface area between the silicide and an upper diffusion layer 1615 becomes smaller along with a reduction in diameter of the pillar-shaped silicon layer, so that an interface resistance between the silicide and the upper diffusion layer is increased to cause deterioration in transistor characteristics.
Secondly, in view of a reduction in the number of steps in an SGT production process, it is desirable to simultaneously form two contacts on respective ones of the upper diffusion layer 1615 and a lower diffusion layer 1614. In this case, the contact 1616 to be formed on top of the pillar-shaped silicon layer has to undergo overetching to an extent corresponding to a height dimension of the pillar-shaped silicon layer or more, as compared with the contact to be formed on the lower diffusion layer 1614. In the SGT structure illustrated in FIG. 48, the contact to be formed on top of the pillar-shaped silicon layer is excessively overetched during etching for the contacts, so that a short-circuiting between the gate and the contact becomes more likely to occur.